1. Field of the Invention
This invention relates to the testing of integrated circuits and, more particularly, to the testing of integrated circuits for wafer sort operations and for functionality test operations following IC packaging.
2. Description of the Relevant Art
The fabrication of integrated circuit dies on semiconductor wafers requires many sophisticated processes. The actual number of processing steps required varies upon the type and complexity of the circuit being built.
After fabrication, the dies of each wafer are separated into individual chips for mounting and connection in a package. The mounting and connecting (bonding) steps are expensive and can approach or exceed the cost of fabrication. Despite various efforts to improve circuit yield, a major reality of semiconductor circuit manufacturing is a sizable percentage of nonfunctioning circuit dies on each wafer. Thus, to avoid wasteful packaging, a test to identify nonfunctioning chips is performed during an operation known as wafer sort (also known as die sort or electrical test). FIG. 1A is a cross-sectional view of a generalized wafer sort system. To perform the test, a wafer 10 is positioned in a wafer sort prober apparatus 12 such that the bonding pads of a particular die are contacted by a series of metal probes 13. During contact by the probes, the die is electrically tested for DC parameters and functionality. The actual electrical testing is directed by a computer 14 connected to the wafer sort prober apparatus 12 and may take from one second to over several seconds. After the test of a die is completed, the wafer sort prober apparatus 12 automatically repositions the wafer such that the pads of another die can be contacted by the metal probes 13 for identical electrical testing. Nonfunctioning or out-of-spec circuits are automatically marked during the procedure with a drop of ink by the wafer sort prober apparatus 12. FIG. 1B is a topological drawing that illustrates the wafer 10 before 10A, during 10B, and after 10C the wafer sort operation.
At the conclusion of the fabrication process and the wafer sort operation, the functioning dies 10D (those not marked with ink) are cut from the wafer and are still vulnerable to contamination and devoid of electrical connectors. Thus, before the chips can be incorporated in a computer or other electrical circuit, the chip must be mounted in a package and connected to the "outside" world via package connections. Typical packages include plastic dual in-line packages (PDIP) and plastic leaded chip carrier (PLCC) packages. FIG. 1C is a perspective view of a plastic dual in-line packaged IC 15 and FIG. 1D is a perspective view of a plastic lead chip carrier packaged IC 16.
Following packaging, another test is performed upon the integrated circuit. This test may include verification of tests performed previously during wafer sort, as well as more exhaustive functional testing, such as testing of the IC under hot and cold temperature conditions.
Referring next to FIG. 2, a typical wafer sort hardware configuration is illustrated that includes the Teradyne A500 or A520 mixed signal test system 20, a sort probe interface board (PIB) 30, an Electroglas 2001X prober apparatus 40, and a probe card 50. The sort probe interface board 30 is mechanically connectable to prober apparatus 40 by way of bolts and provides customized connections between the probe card 50 and the test system 20. When the system is setup in its operational configuration, both the probe interface board 30 and the probe card 50 are positioned on prober apparatus 40. As will be described in greater detail below, test system 20 includes a test head that can be latched and secured against a top side of probe interface board 30. The probe card 50 is positioned in prober apparatus 40 to contact the bottom side of the probe interface board 30 such that the probe interface board 30 is sandwiched between the test head and the probe card 50. The other side of probe card 50 includes a series of probes that make electrical contact with the wafer 10. The wafer 10 is precisely positioned in its testing location by prober apparatus 40. A plurality of additional wafers are positioned within a cassette unit of prober apparatus 40 to await similar positioning and testing. During subsequent tests, the prober apparatus 40 automatically removes each wafer from the cassette and precisely positions it beneath the probe card 50 such that the series of probes contact a particular dye on the wafer. The prober apparatus 40 is initially calibrated by means of a microscope 41 that facilitates visual inspection and alignment of the wafer. It is noted that probe interface board 30 includes a hole in its center to accommodate this visual access through the system to the wafer 10.
FIG. 3 is an expanded view of the Teradyne A520 mixed signal test system 20. The test system includes a mainframe portion having a mixed signal cabinet 21, an analog cabinet 22, and test and user computers supplied by Sun Microsystems, Inc. The test system 20 further includes a terminal and monitor combination 23, a power supply vault 24, and a test head assembly (shown in FIG. 4). The mixed signal cabinet 21 contains the digital subsystems and a mixed signal test head interface. The analog cabinet 22 contains the analog subsystems, the analog test head interface and a test computer. The A520 test system 20 provides primary control over a large variety of test operations to perform both wafer sort and packaged IC tests.
FIG. 4 is a perspective view of a test head assembly integrated with the A520 test system 20. The mainframe of the test system 20 is connected to the test head assembly through multiple cables which originate on the operator side of the mainframe. The test head assembly includes a test head 25 mounted to a stand 26 that is movable upon a set of rollers 29. The test head 25 is mounted on an arm of stand 26 and can be rotated in a counterclockwise direction "a" or in a clockwise direction "b". The test head 25 provides an interface between the probe interface board 30 (FIG. 2) and the mainframe of the A500 test system 20. Test head 25 is rotatable upon stand 26 to accommodate mechanical connection to prober apparatus 40 (FIG. 2) as well as to various IC handler apparatus, as will be described further below.
FIG. 5 is an expanded block diagram of test head 25 of the test head assembly. The test head 25 includes linking circuitry to maintain the integrity and fidelity of signals propagating to and from the device under test (e.g., wafer 10). Both analog and digital channel electronics are provided to carry low-distortion analog signals and high-frequency digital signals from the test system 20 to the device under test. The test head 25 includes a base 26 that houses a test head card cage 26A and a plurality of test head channel cards 26B. The channel cards 26B plug into the test head card cage 26A and supply the local electronics required to interface to the device under test. A channel card interface board 27 and a connector board 28 provide an interface between the device under test and the channel cards 26B in the station base 26. Connector board 28 is a printed circuit board that is connected to the channel card interface board 27 via coaxial cables 28B. The top side of connector board 28 includes a ring of spring-loaded contact pins 28A, also referred to as ISO-pins or POGO-pins, that contact and make electrical connections to an interface board 30A (such as probe interface board 30 or a device interface board described below).
FIG. 6 illustrates an expanded view of the probe interface board 30. The probe interface board 30 includes a metal frame 31 that provides mechanical support and mounting for a printed circuit board 32. As explained previously, a center portion 33 is cut out or left open to allow visual inspection and alignment of a semiconductor wafer that will be positioned beneath the board in the prober apparatus 40. The printed circuit board 32 provides customized connections between the A520 test head assembly and the probe card 50 (FIG. 2). The specific layout of printed circuit board 32, as well as associated electrical components such as relays and capacitors connected thereto, are customized by the user for proper adaptation to the specific integrated circuits that are to be tested. The printed circuit board 32 includes a test head interface area 34 as well as a probe card interface area 35 each extending circumferentially around opposite surfaces of the printed circuit board 32. The test head interface area 34 includes a series of contact pads formed on the printed circuit board 32 that mate with the spring-loaded contact pins 28A of the board 28 incorporated within the test head 25 (FIG. 5). The probe card interface area 35 contains a similar series of contact pads that mate with spring-loaded contact pins on probe card 50, as will be described further below.
FIG. 7 is a bottom-side view of probe card 50. Probe card 50 includes a plurality of interconnect lines 51 formed on and extending from a printed circuit board 52. The interconnect lines 51 extend radially from a center contact portion where electrical contact can be made to the pads of a die on a semiconductor wafer. The topside of probe card 50 (not shown) includes a plurality of spring-loaded contact pins that mate with the circumferential contact pads of the probe card interface area 35 of probe interface board 30 (FIG. 6). During a wafer sort operation, the probe card 50 is positioned within prober apparatus 40 (FIG. 2) and provides an electrical pathway between the probe interface board 30 and the wafer 10.
From the foregoing descriptions of FIGS. 2-7, it is evident that an electrical pathway and interface is established between the semiconductor wafer 10 and the test system 20. As a summary, the test system 20 includes a test computer that controls primary test operations performed upon the semiconductor wafer 10. The probe interface board 30 provides a custom interface between the wafer 10 and the test system 20 and includes a hole in its center. The probe card 50 and the probe interface board 30 are both positioned on the prober apparatus 40 such that the spring-loaded contactor pins of probe card 50 make electrical connections to the probe card interface area 35 of probe interface board 30. The prober apparatus 40 includes a microscope 41 to view the wafer 10 through the center hole portions of the sort probe interface board 30 and the probe card 50 to allow visual inspection and alignment of the wafer 10. The test head assembly is then latched to the probe interface board 30 to complete the test set-up. After the prober apparatus 40 has been calibrated, subsequent dies and wafers are automatically positioned by prober apparatus 40 for contact with probe card 50. Following each sort operation, non-functional dies are marked with ink by an inking device incorporated on prober apparatus 40.
The testing of integrated circuits after packaging will next be considered. FIG. 8 illustrates a typical hardware configuration for testing PDIP packaged integrated circuits. The system includes a Teradyne A500 or A520 test system (same as that described above), a device interface board (DIB) 60, a docking plate 70, a packaged IC handler apparatus 75, a second packaged IC handler apparatus 80, an IC contactor unit 85, and a second IC contactor unit 90. Handler apparatus 75 is a hot and room temperature handler manufactured by Micro Component Technology, Inc. (MCT), St. Paul, MN, Model No. 3616E. The associated IC contactor 85 is an elevated and ambient temperature contactor also manufactured by MCT, Model No. 116142. The handler apparatus 80 is a cold and room temperature handler, MCT Model No. 3608C, and IC contactor 90 is a cold and ambient temperature contactor, MCT Model No. 945384. Each of these components will be better understood from the following description.
FIG. 9 illustrates a bottom view of device interface board 60. The device interface board 60 is similar to the probe interface board 30 in that it provides an interface to the test head assembly of test system 20. The topside (not shown) of device interface board 60 includes a metal frame that provides mechanical support for the main body of the device interface board 60. The main body of the device interface board 60 is composed of a printed circuit board 62 that provides customized connections between the A520 test head assembly and an IC contactor unit 85 or 90. The specific layout of the printed circuit board 62 as well as the electrical components connected thereto are customized by the user for proper adaptation to the specific integrated circuits that are to be tested. The printed circuit board 62 includes a test head interface area 64 that includes a series of contact pads formed circumferentially around the surface of the printed circuit board 62. These contact pads are formed to mate with the spring-loaded contact pins 28A of the connector board 28 incorporated within the test head 25 (FIG. 5). A female connector 65 is provided near the center of the device interface board 60 on its opposite side to provide a connecting mate for either the IC contactor 85 or IC contactor unit 90. It is noted that the device interface board 60 does not have a hole in its center.
FIG. 10 illustrates a perspective view of an IC contactor unit 86 representative of IC contactors 85 and 90. IC contactor unit 86 includes an IC receiving port 87 that receives a packaged integrated circuit. A plurality of pins 88 of the IC contactor unit 86 individually contact the pins of the integrated circuit. The other side (not shown) of the IC contactor unit 86 includes a plurality of male connector pins that mate to the female connector 65 of the device interface board 60.
Referring back to FIG. 8, IC contactors 85 and 90 are bolted to a rear portion of the handlers 75 and 80, respectively. The docking plate 70 is also bolted to a rear portion of the handler 75 or 80 such that the male connecting pins of the respective IC contactor 85 or 90 are exposed through a center hole of the docking plate 70. The device interface board 60 can then be bolted to the docking plate 70 such that the male connector pins of the IC contactor 85 or 90 are received by the female connector 65 of device interface board 60. Setup of the hardware configuration is completed by latching the test head of the A520 test system to the device interface board 60. Upon completion of the setup, packaged IC testing can be initiated. It is noted that handler apparatus 75 and 80 are provided to automatically position individual packaged integrated circuits into the contactor units 85 and 90 for automatic testing. Hundreds of packaged integrated circuits can be inserted within the respective handler apparatus at the same time and are each automatically positioned in turn within the respective IC contactor 85 or 90. Following the test of each integrated circuit, the handler apparatus 75 or 80 categorizes and separates the functioning integrated circuits from the nonfunctioning integrated circuits.
FIG. 11 shows a similar hardware configuration for testing PLCC packaged integrated circuits. The configuration of FIG. 11 is similar to that of FIG. 8 and includes a handler apparatus 91 manufactured by Aetrium, Inc., St. Paul, MN, Model No. 3100. An IC contactor 92 is provided that mounts to the rear of the handler apparatus 91 and includes a receptacle to receive PLCC packaged integrated circuits. A device interface board 93 interfaces with a rear connector portion of IC contactor 92 and the test head of test system 20.
It is not surprising that the components of the test configurations as shown in FIGS. 2-11 are extremely expensive. Each probe interface board 30 and device interface board 60 can cost several thousands of dollars alone. The probe interface board 30 is designed to accommodate the spring-loaded contact pins of the probe card 50 and must include a hole to facilitate visual inspection and alignment of the wafer. On the other hand, the device interface board 60 is designed to accommodate the male pins of the IC contactor 85 or 90 near the center of the device interface board 60. Due to these independent and conflicting design considerations, the probe interface board 30 and the device interface board 60 are quite different in design and are incompatible with one another. The semiconductor manufacturer must therefore incur the costs of both types of boards to perform both wafer sort operations and packaged IC testing.
An additional problem associated with the wafer sort hardware configuration of FIG. 2 occurs when the test configuration itself is malfunctioning due to, for example, faulty software within test system 20, faulty interface circuitry, or damaged components and interconnect lines. Since both the probe interface board 30 and the probe card 50 must be positioned within prober apparatus 40, debugging of the probe interface board 50 is difficult due to inadequate mechanical clearance for the test probes of oscilloscopes and other debugging equipment.